The present invention relates to a vector processor, and more particularly to a vector processor for effectively controlling memory access while avoiding a memory bank conflict by effecting byte-by-byte data transfer between a vector register and an operation unit.
When image processing or information processing pertaining to artificial intelligence is to be effected in a data processor, a byte-by-byte memory accessing function is usually required.
A vector processor, having a high data processing ability, may use a plurality of operation units in an overlapped fashion by a utilizing a chaining function. In the vector processor, the memory accessing is effected not by byte but by word or double words in order to attain a high data processing ability.
In a scientific and technical calculation, most processings are effected by word or double words. Further high speed processing is attained by a memory access control system.
On the other hand, in image processing, the processing is effected by byte and hence it is difficult to attain a high processing speed by the memory access control because of memory bank conflict.
Memory accessing means for the vector processor for accessing by byte in order to solve the above problem is disclosed in JP-A-60-186964.
It is very difficult to implement access to the memory by byte while avoiding an increase in the amount of hardware.
For example, the physical quantity of the hardware may be considerably small if data are stored in successive addresses even if the is of byte dimensions. However, in information processing pertaining to artificial intelligence, it is difficult to store the data in the successive addresses.
In the prior art vector processor in which the image processing is effected byte by byte, it is difficult to attain high speed processing because memory bank conflict occurs during the memory access control.